Sim time08:00:00
Speed60×
Shift A · Day 1

Line Topology

13 stations · 8 cell-side · 5 module-side

Cell side (wafer → tested cell)

#1
Wafer Inspection
×4 · 1.5s
WIP 0
→
#2
Texturing
×1 · 600s
WIP 0
→
#3
Cleaning (RCA)
×1 · 180s
WIP 0
→
#4
PECVD a-Si:H
×6 · 240s
WIP 0
HERO
→
#5
TCO Sputter (PVD)
×4 · 180s
WIP 0
HERO
→
#6
Screen Print
×4 · 4s
WIP 0
→
#7
Curing (LT)
×2 · 90s
WIP 0
→
#8
Cell Test (I-V)
×8 · 1.2s
WIP 0

Module side (cell → finished module)

#9
Stringing
×6 · 80s
WIP 0
HERO
→
#10
Layup
×4 · 45s
WIP 0
→
#11
Lamination
×3 · 480s
WIP 0
HERO
→
#12
Framing & J-Box
×4 · 90s
WIP 0
→
#13
Final Test (Flash + EL)
×4 · 30s
WIP 0
HERO

Bottleneck analysis

Highest queue: wafer-insp with 0 WIP units.
Theoretical max throughput is gated by the slowest station's parallelism × cycle time.